1. Field of the Invention
The present invention relates to a plasma display panel, and more particularly, to an energy recovery apparatus of a plasma display panel and method thereof.
2. Description of the Background Art
A plasma display panel (hereinafter, referred to as a ‘PDP’) is adapted to display an image including characters or graphics by light-emitting phosphors with ultraviolet having a wavelength of 147 nm generated during the discharge of an inert mixed gas such as He+Xe, Ne+Xe or He+Ne+Xe. This PDP can be easily made thin and large, and it can provide greatly increased image quality with the recent development of the relevant technology. Particularly, a three-electrode AC surface discharge type PDP has advantages of lower driving voltage and longer product lifespan as a wall charge is accumulated on a surface in discharging and electrodes are protected from sputtering caused by discharging.
FIG. 1 is a perspective view showing the configuration of a discharge cell of a conventional plasma display panel. Referring now to FIG. 1, the discharge cell of the conventional plasma display panel includes a scan electrode Y and a sustain electrode Z which are formed on the bottom surface of an upper substrate 10, and an address electrode X formed on a lower substrate 18. Each of the scan electrode Y and the sustain electrode Z includes transparent electrodes 12Y and 12Z, and metal bus electrodes 13Y and 13Z which have a line width smaller than that of the transparent electrodes 12Y and 12Z and are respectively disposed at one side edges of the transparent electrodes.
The transparent electrodes 12Y and 12Z are typically formed using indium-tin-oxide (hereinafter, referred to as ‘ITO’) on the upper substrate 10. The metal bus electrodes 13Y and 13Z are formed on the transparent electrodes 12Y and 12Z usually using a metal such as chromium (Cr) and serve to reduce a voltage drop by the transparent electrodes 12Y and 12Z having high resistance. An upper dielectric layer 14 and a protection film 16 are laminated on the upper substrate 10 in which the scan electrode Y and the sustain electrode Z are formed in parallel. Wall charges generated upon the plasma discharge are accumulated on the upper dielectric layer 14. The protection film 16 serves to prevent damage of the upper dielectric layer 14 due to sputtering occurred upon the plasma discharge and to increase emission efficiency of secondary electrons. The protection film 16 is typically formed using magnesium oxide (MgO).
A lower dielectric layer 22 and barrier ribs 24 are formed on the lower substrate 18 in which the address electrode X is formed. A fluorescent material layer 26 is covered on the lower dielectric layer 22 and the barrier ribs 24. The address electrode X is formed in the direction to intersect the scan electrode Y and the sustain electrode Z. The barrier ribs 24 are formed in a stripe or lattice type and serve to prevent ultraviolet rays and a visible ray generated due to the discharge from leaking toward neighboring discharge cells. The fluorescent material layer 26 is excited by ultraviolet rays generated upon the plasma discharge to generate any one visible ray of red, green and blue lights. Inert mixed gases are inserted into a discharge space defined between the upper/lower substrates 10 and 18 and the barrier ribs 24.
This three-electrode AC surface discharge type PDP is divided into a plurality of sub-fields and is driven. In the period of each of the sub-fields, lights are emitted by the number proportional to a weighted value of video data, thereby displaying the gray level. The plurality of sub-fields are sub-divided into a reset period, an address period, a sustain period and a blanking period, and are driven.
In the above, the reset period is a period for forming an uniform wall charge on the discharge cell, the address period is a period for generating an selective address discharge according to a logical value of the video data, and the sustain period is a period for maintaining discharge in the discharge cell from which the address discharge is generated.
An address discharge and a sustain discharge of the AC surface discharge type PDP driven thus require high voltage of more than several hundreds of volts. Thus, in order to minimize the driving power necessary for the address discharge and the sustain discharge, an energy recovery apparatus is used. The energy recovery apparatus is adapted to recover a voltage between the scan electrode Y and the sustain electrode Z and to use the recovered voltage as a driving voltage for a subsequent discharge.
FIG. 2 is a circuit diagram showing an energy recovery apparatus formed on the scan electrode Y for recovering a voltage of the sustain discharge. Practically, the energy recovery apparatus is placed symmetrically to the sustain electrode Z with respect to a central panel capacitor (Cp).
Referring to FIG. 2, a conventional energy recovery apparatus includes an inductor L connected between a panel capacitor Cp and a source capacitor Cs, a first switch S1 and a third switch S3 which are connected in parallel between the source capacitor Cs and the inductor L, diodes D5 and D6 which are disposed between the first and third switches S1, S3 and the inductor L, and a second switch S2 and the fourth switch S4 which are connected in parallel between the inductor L and the panel capacitor Cp.
The panel capacitor Cp represents equivalent capacitance formed between the scan electrode Y and the sustain electrode Z. The second switch S2 is connected to a reference voltage source Vs, and the fourth switch S4 is connected to a ground voltage source GND. The source capacitor Cs recovers and charges the voltage which is charged in the panel capacitor Cp during sustain discharging, and provides again the charged voltage to the panel capacitor cp.
To this end, the source capacitor Cs has a capacitance capable of charging the voltage of Vs/2 that corresponds to a half of the reference voltage source Vs. The inductor L forms a resonant circuit together with the panel capacitor Cp. The first to fourth switches S1 to S4 control the flow of current. The fifth diode D5 and the sixth diode D6 both prevent the flow of electric current from reversing. Further, the internal diodes D1 to D4 each disposed within the first to fourth switches S1 to S4 also prevent the flow of electric current from reversing.
FIG. 3 is a timing showing ON/OFF timings of the switches and a waveform diagram showing output waveforms of the panel capacitors of FIG. 2.
The operation procedure will now be explained on the assumption that the panel capacitor Cp is charged with a voltage of 0 volt and the source capacitor Cs is charged with a voltage of Vs/2 before a period of T1.
In a period of T1, the first switch S1 is turned on, so that an electric current path is formed from the source capacitor Cs to the panel capacitor Cp through the first switch S1 and the inductor L. When the electric current path is formed, the voltage of Vs/2 charged in the source capacitor Cs is supplied to the panel capacitor Cp. In this time, the inductor L and the panel capacitor Cp form a serial resonant circuit, so that the panel capacitor Cp is charged with the voltage of Vs that is twice the voltage of the source capacitor Cs.
In a period of T2, the second switch S2 is turned on. When the second switch S2 is turned on, the panel capacitor Cp is provided with the voltage of the reference voltage source Vs. That is, when the second switch S2 is turned on, the voltage of the reference voltage source Vs is supplied to the panel capacitor Cp, which prevents that the voltage value of the panel capacitor Cp falls below that of the reference voltage source Vs, thereby generating a stable sustain discharge. At this time, since the voltage of the panel capacitor Cp rises up to Vs during the period of T1, the voltage value that is supplied from the outside during the period of T2 can be minimized. That is, it is possible to reduce power consumption.
In a period of T3, the first switch S1 is turned off. In this time, the panel capacitor Cp maintains the voltage of the reference voltage source Vs. In a period of T4, the second switch S2 is turned off and the third switch S3 is turned on. When the third switch S3 is turned on, an electrical current path is formed from the panel capacitor Cp to the source capacitor Cs through the inductor L and the third switch S3, and the source capacitor Cs recovers the voltage that is charged in the panel capacitor Cp. In this time, the source capacitor Cs is charged with a voltage of Vs/2.
In a period of T5, the third switch S3 is turned off and the fourth switch S4 is turned on. When the fourth switch S4 is turned on, an electric current path is formed between the panel capacitor Cp and the ground voltage source GND, and the voltage of the panel capacitor Cp drops to 0 volt. In a period of T6, a state of T5 remains for a given time period. Practically, an AC driving pulse that is supplied to the scan electrode Y and the sustain electrode Z may be obtained as the periods of T1 to T6 are periodically cycled.
However, a large amount of manufacturing cost is required in order to fabricate this conventional energy recovery apparatus. That is, elements (a diode, a switching element, etc.) used in the conventional energy recovery apparatus should have an internal voltage that can withstand the voltage value of the reference voltage source Vs. Further, the fifth and sixth diodes D5 and D6 must have a rapid response speed. Therefore, since lots of elements having a rapid response speed and a high internal voltage are employed in a prior art, manufacturing cost is high.